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Course Project Information

Presentation Schedule:

NOTE: Each project has 10 mins to present. Please email your slides to sitaoh@uci.edu before class. 

3/14 (Tuesday):

  • Karim Barada: Compiler-Assisted GPU Optimizations
  • Ziang Chen: Hardware Acceleration for Edge Computing with AI engagement
  • Bhavya Chunchu: Debugging techniques and tools for Hardware Accelerators
  • Timothy Do: FPGA-Based Image Accelerators for Optimizing Convolutional Operators
  • Yaoze Zhang, Zhipei He: AES Algorithm Accelerator by Using HLS Tools
  • Asma Khan: Compilers for DNN Accelerators

Survey link for Tuesday Presentations: https://forms.gle/9wdPcZfsAo9PqGJf7 Links to an external site.

 

3/16 (Thursday):

  • Shengqi Li: FPGA-based Deep Neural Network Accelerators
  • Xinyi Tang, Yiming Shen: Review of Phase-Locked Loops (PLLs) Based on FPGAs
  • Mrudul Shailesh Sonawane: Dynamic and Partial Reconfigurability of FPGA
  • Yuanzhe Zhang, Jinwen Wu: The Optimization of Matrix Multiplication
  • Haocheng Xu: HLS-RISC: High-Level Synthesis For RISC-V AI/ML Accelerator
  • Valen Yamamoto: Design Space Exploration of For Loops in PyLog for High Level Synthesis

Survey link for Thursday presentations: https://forms.gle/evykbP4DWBLYrsCL6 Links to an external site.

 

Final Report

  • Double-column, use ACM conference paper template Links to an external site.. 
  • Suggested length: single-student project: 4 or more pages, two-student project: 6 or more pages.
  • Include links to your source code (if any)
  • Please proofread your report before submission
  • General expectation: research-paper quality

 

Grading: 

  • 40% of the total course final grade
  • Proposal (10%) + Presentation & Report (30%)

 

Report Content: 

(for option (a) literature review projects: )

  • Title
  • Abstract
  • Introduction (background, motivation, topic ranges of your review, etc.)
  • Contribution (the unique contributions of your review, how will your review benefit future researchers)
  • Detailed reviews of various topics/sub-fields/categories
  • Summary
  • Future research opportunities in the field
  • List of references

 

(for option (b) compiler & accelerator projects: )

  • Title
  • Abstract
  • Introduction (background, motivation, problem definition, etc.)
  • Contribution (the unique contributions of your project, how will your work benefit future researchers)
  • Related Works
  • Your Approach/Method
  • Experimental Results
  • Conclusion
  • Future Works
  • List of references

 

Grading Rubrics: 

(for option (a) literature review projects: )

  • Workload (20%)
  • Coverage/Completeness of the review (20%)
  • Discussion in the review (20%)
  • Technical contribution (10%)
  • Presentation/Report quality (30%)

 

(for option (b) compiler & accelerator projects: )

  • Workload (20%)
  • Completeness (20%)
  • Technical contribution/novelty (20%)
  • Reproducibility/technical soundness (10%)

 

Winter 2022 Projects: 

  • Hardware Accelerator Architecture for Imaging Tracking (Yun-Hsuan Kuo)
  • Review of  DNN accelerators based on FPGA (Xiaofang Zhang)
  • A Universal FPGA Reconfigurable Computing Schema (Zeqiang Zheng)
  • FPGA Overlay Architectures (Kenny Tang)
  • Reversible water marking (using VHDL) (Kartik Jain, Mansi Chauhan)
  • Optimization of hls4ml: an automatic NNs-to-HLS translation workflow (Yifan Zhang, Yuhui Li)
  • A Compiler for Associate Processors (Rachid Karami, Mariam Rakka)
  • FIR Hardware Accelorators (Calder Staude)
  • Comparison of the performance between the HLS tools and manually RTL code (Hongzheng Tian)
  • HLS Debugging and Verification: literature review (Tianyu Yu)
  • RaTriCounter: solution to solving Triangle-Counting (Yoonha Cha, Seongyoung Kang)
  • Review of Resistive Memory-based Accelerators on Neural Networks Training and Inference (Ye Qiao, Andrew Ding)