Course Modules

VHDL

VHDL
Module Completed Module In Progress Module Locked
VHDL 6215  
  • Attachment
    Combinatiobal-circuit-1.pdf Combinatiobal-circuit-1.pdf
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    Combinatiobal-circuit-2.pdf Combinatiobal-circuit-2.pdf
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    Sequential Circuit.pdf Sequential Circuit.pdf
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    vhdl_ref.zip vhdl_ref.zip
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    vhdl-1.chm vhdl-1.chm
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete

Verilog

Verilog
Module Completed Module In Progress Module Locked
Verilog 6216  
  • Attachment
    verilog_ref.zip verilog_ref.zip
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    verilog-1.chm verilog-1.chm
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    systemverilog-lrm.pdf systemverilog-lrm.pdf
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    systemverilog.pdf systemverilog.pdf
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete

Coding examples

Coding examples
Module Completed Module In Progress Module Locked
Coding examples 6234  
  • Attachment
    Preloading_Memory_VHDL.zip Preloading_Memory_VHDL.zip
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    memory_preloading.tar memory_preloading.tar
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    lecture-5-synthesis.tar lecture-5-synthesis.tar
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    regfile_synthesis.tar regfile_synthesis.tar
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • External Url
    Synthesizing SRAM Memory Synthesizing SRAM Memory
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete

Extra Materials

Extra Materials
Module Completed Module In Progress Module Locked
Extra Materials 6515  
  • External Url
    MIPS Assemby MIPS Assemby
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
  • Attachment
    coding_guidelines.pdf coding_guidelines.pdf
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
 
minimum score must view must submit must contribute