Course Syllabus

Jump to Today

Course Description

EECS 31L Introduction to Digital Logic Design Laboratory (3)
This is a laboratory course in which students learn the design process of modeling, simulation and synthesis of simple digital designs. Students in this class learn how to model designs with a hardware description language, Verilog/SystemVerilog.
Prerequisites: (EECS 31 OR CSE 31)
                              and
                         (EECS 10 OR EECS 12 OR CSE 22 OR I&C SCI 22 OR CSE 42 OR I&C SCI 32)

Course Outcome/Performance Criteria

Course objectives represent what the course strives to accomplish.
Course outcomes represent what will be measured to determine if the course met its objectives.
Course outcomes relate to a subset of the program outcomes.

  • Course goals

    • Understand the principles and methodology of digital logic design at the gate and switch level, including both combinational and sequential logic elements.
    • Gain experience developing a relatively large and complex digital system.
    • Gain experience with modern computer-aided design tools for digital logic design.
    • Understand clocking methodologies used to control the flow of information and manage circuit state.
    • Appreciate methods for specifying digital logic, as well as the process by which a high-level specification of a circuit is synthesized into logic networks.
    • Appreciate the trade-off between hardware and software implementations of a given function.

  • Course Outcomes:

    • Students will read given source code in HDL and understand its behavior (EAC k)
    • Students will be able to extend existing source code for new features (EAC a, e, k)
    • Students will be able to write original source code in hardware to develop a digital block (EAC a, e, k)
    • Students will be able to organize source code in a modular form (EAC k)

  • Related Program Outcomes:

    • (EAC a) an ability to apply knowledge of mathematics, science, and engineering
    • (EAC e) an ability to identify, formulate, and solve engineering problems
    • (EAC k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice

Grading Policy

Parts Share
Final Project
30%
FPGA Showcase
 25%
Midterm Project
 20%
Quiz
 25%

Course Resources

Course policies

  • You are expected to check the course website daily for assignments and announcements.

  • Attendance Policy:

    Attendance at lecture and laboratory sections is expected.
    It is the student's responsibility to make up for any missed instruction.
    Make-up assignments and/or exams will only be arranged for absence due to medical (or similar) reasons. Proper documentation is required.

  • Laboratory Policy:

    You are required to bring your own laptop.
    You are supposed to attend the enrolled lab section. You are free to attend the other lab sections as long as there are free seats available. They are offered strictly for your benefit. Please attend the same lab section every week.

  • Homework/Assignments/Projects:

    There is no late policy - late assignments are not accepted. For all re-grades, submit a written request to the instructor. All submissions are re-graded entirety, potentially resulting in a lower overall score.

  • Exams:

    You are required to read the electronic reference and take all the quizzes and questions/Problems.

  • Academic Honesty:

    The complete policy statement on Academic Honesty is published in the UCI Schedule of Classes, Fall Quarter 2017.
    Under no circumstances are students allowed to work together on any of the examinations.
    Dishonesty includes false representation of course work, including but not limited to cheating on an exam, fraudulently presenting lab exercises or assignments by someone else as one's own, or getting someone else to take the course.
    Do not copy code! This is a serious offense that will not be tolerated in this course.
    Dishonesty will be reported and punished under University regulations.

This page has been viewed [counter] times.

Course Summary:

Date Details Due