Welcome to EECS 31L: Introduction to Digital Logic Laboratory (Spring 2024)!

Instructor: Sitao Huang (sitaoh@uci.edu)

Office Hours: Thursdays 9-10am (EH 3225) or by appointment

Lecture Time: Mondays/Wednesdays/Fridays 12-12:50 pm

Lecture Location: SSH 100

TAs:

Graders:

Labs:

Week	Lecture	Slides	Recordings
1	Introduction	lec1-introduction.pdf	4/1, 4/3, 4/5
2	Verilog Basics	lec2-verilog-basics.pdf	4/8, 4/10, 4/12
3	Combinational Logic and Sequential Logic	lec3-sequential-logic.pdf	4/15, 4/17, 4/19
4	Processor Design Basics	lec4-basic-processor.pdf	4/22, 4/24, 4/26
5		Midterm	4/29, 5/1, 5/3
6	Finite State Machine (FSM)	lec5-finite-state-machine.pdf	5/6, 5/8, 5/10
7	Tasks and Functions Synthesis Basics	lec6-tasks-and-functions.pdf lec7-synthesis.pdf	5/13, 5/15, 5/17
8	SystemVerilog Basics	lec8-systemverilog-basics.pdf lec9-systemverilog-verification.pdf	5/20, 5/22, 5/24 (zoom no slides)
9	VHDL	lec10-vhdl.pdf	5/29, 5/31
10	FPGA and HLS	lec11-fpga-hls.pdf	6/3, 6/5, 6/7