Course Syllabus

Course Description

Course Outcome/Performance Criteria

Course objectives represent what the course strives to accomplish.
Course outcomes represent what will be measured to determine if the course met its objectives.
Course outcomes relate to a subset of the program outcomes.

• Course goals

  • Understand the principles and methodology of processor design.
  • Gain experience developing a relatively large and complex digital system.
  • Gain experience with modern computer-aided design tools for digital logic design.
  • Understand clocking methodologies used to control the flow of information and manage circuit state.
  • Appreciate methods for specifying digital logic, as well as the process by which a high-level specification of a circuit is synthesized into logic networks.

• Course Outcomes:

  • Students will be able to write structured, multi-module hardware models in SystemVerilog. (CAC a, CAC i, CAC j, EAC e, EAC h)
  • Students will be able to compile SystemVerilog files using a CAD tool such as MentorGraphics QuestaSim that involve external libraries. (CAC a, CAC i, CAC j, EAC e, EAC k)
  • Students will be able to test and debug programs using a simulator such as MentorGraphics or Cadence. (CAC a, CAC i, CAC j, EAC e, EAC k)
  • Students will be able to analyze waveforms for correctness and efficiency. (CAC a, CAC i, CAC j, EAC e, EAC k)

• Related Program Outcomes:

  • (EAC a) an ability to apply knowledge of mathematics, science, and engineering
  • (EAC e) an ability to identify, formulate, and solve engineering problems
  • (EAC k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice

Grading Policy

Parts	Topic	Share
Assignment-1	Single-Cycle Processor Verification	0%
Assignment-2	Complete Single-Cycle Processor + Synthesis	35%
Assignment-3	Pipeline Processor	45%
Quiz	TopHat Questions	20%

Course Resources

• Course web site
  online at here

• Text book

• Supplemental book

	David A. Patterson and John L. Hennessy: Computer Organization and Design RISC-V Edition: The Hardware Software Interface, The Morgan Kaufmann Series in Computer Architecture and Design ISBN-13: 978-0128122754
	strong>David A. Patterson and John L. Hennessy: Computer Architecture, Sixth Edition: A Quantitative Approach, 6st Edition, ISBN-13: 978-0128119051

• Supplemental books

Course policies

• You are expected to check the course website daily for assignments and announcements.

• Attendance Policy:

  Attendance at lecture and laboratory sections is expected.
  It is the student's responsibility to make up for any missed instruction.
  Make-up assignments and/or exams will only be arranged for absence due to medical (or similar) reasons. Proper documentation is required.

• Laboratory Policy:

  You are required to bring your own laptop in lab sessions.
  You are supposed to attend the enrolled lab section. You are free to attend the other lab sections as long as there are free seats available. They are offered strictly for your benefit. Please attend the same lab section every week.

• Assignments:

  There is no late submission policy - late assignments are NOT accepted. The course material and project work in EECS 112L builds on itself, so be careful not to fall behind. Catching up is extremely difficult, especially as other coursework picks up mid-quarter.
  For all re-grades, submit a written request to the instructor within ONE week. All submissions are re-graded entirety, potentially resulting in a lower overall score.

• Exams:

  The course includes no midterm/final examination (subject to change). But there are quiz questions.
  Each quiz covers all the material discussed in the course until the day of the examination.

• Academic Honesty:

  The complete policy statement on Academic Honesty is published in the UCI Schedule of Classes, Winter Quarter 2018.
  Under no circumstances are students allowed to work together on any of the examinations.
  Dishonesty includes false representation of course work, including but not limited to cheating on an exam, fraudulently presenting lab exercises or assignments by someone else as one's own, or getting someone else to take the course.
  Do not copy code! This is a serious offense that will not be tolerated in this course.
  Dishonesty will be reported and punished under University regulations.